DOCUMENT ID: 1325-02

SYNOPSIS:    A description of Hardware Memory Management

OS RELEASE:  2.4

PRODUCT:     Solaris     

KEYWORDS:    hardware memory processor mmu cache buffer


DESCRIPTION:

Basics of Hardware Memory Management



                        Hardware Memory Managment

System Model

Uniprocessor:

                            Main memory
                                MMU
                CPU            Cache            I/O
                 |               |               |
                 |               |               |
                  --------------------------------


Multiprocessor:


        Module 0        Module 1

          CPU             CPU           Main memory
         Cache           Cache              |
          MMU             MMU               |
         Write           Write              |
        Buffers         Buffers             |
           |               |                |
           |               |                |
            ----------------- Mbus ---------                   
                                        |
                                        |
                                      IOMMU
                                      I/O   (MSI Main Store Interface)



In a uniprocessor system, the CPU and I/O access main memory through a
common MMU (because I/O uses direct memory access (DMA), which goes
through the MMU). 

The Sun-4m supports a number of seperate CPU modules, each of which has
its own MMU and cache.  All modules share main memory. 

Devices use a seperate I/O MMU. 

So as not to block modules wanting to write to memory, each module's
cache uses a write buffer.  The data is written to the buffer; then it
is written to main memory when access to the main bus is granted. 


Virtual-to-Physical Address Translation


     Stack

     -----

     Hole
                                  Physical address
     -----   CPU----------> MMU -------------------> Physical memory
                  Virtual
     Data         address

     -----

     Text

Uniprocessor SPARC(tm) machines use a special MMU.

Memory is divided into segments, and the segments are subdivided into
pages. 

The segments are addressed in a segment table, and each entry points to
a group of page table entries.  A page table entry contains information
about one physical page, such as its physical location and whether it
has been modified. 

A cache is used to speed up the address translation so that multiple
accesses to main memory are not necessary. 

The Sun-4m uses the SPARC reference MMU.


SPARC Reference MMU

A major difference between this MMU and the previous one is that all the
structures (page tables, page table entries) reside in main memory.  The
previous MMU used its own memory.  The reference MMU removes that
restriction, so page tables are only limited by main memory (of course,
this means they compete for space with user processes and file blocks). 


  Page Table Entry (pte)

  A pte contains the following information:

  * Valid bit - indicates that an entry is valid

  * Write bit - indicates write access to a page

  * Supervisor bit - access to a page is restricted to the kernel

  * No-cache-bit - keeps a page from being placed in cache because
    of possible aliasing problems.

  * Reference bit - set when the page is referenced

  * Modify bit - set when the page is changed

  * Physical page number - the high-order bits of the physical
    address


DATE APPROVED: 05/08/95